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MOUNTAIN VIEW, Calif.----October 18, 2000-- Synopsys, Inc. (Nasdaq:SNPS) and STMicroelectronics (NYSE:STM - ) announced today, a multi-phased technology alliance to develop and deploy advanced Design-for-Test (DFT) solutions for complex systems-on-chip (SoC). As an industry leader in system-on-chip design, STMicroelectronics contributes its expertise in this area and will identify new DFT requirements. Synopsys will expand and enhance its industry-leading DFT solutions, which are already in widespread use within STMicroelectronics.

The initial focus of this alliance will be to improve ST's SoC design-for-test flows in order to more quickly and predictably achieving DFT closure. The relationship will provide a high productivity and high quality-of-results (QoR) implementation path from the system level all the way to production silicon. Synopsys will provide new and existing DFT tools for deployment and integration into ST's SoC test analysis, synthesis, pattern generation and verification flows over the course of the next year. These tools will support ST's DFT closure goals from RTL to GDSII, and enable ST to meet the highest test quality requirements by delivering state-of-the art scan, BIST, IDDQ, at-speed testing and fault diagnosis technologies and flows.

``ST is an industry leader in the creation of state-of-the-art systems-on-chip for consumers, including set-top box, wireless, wireline and automotive applications, and our experience is that the manufacturing test challenges for SoCs are particularly difficult. We also strive for extremely high quality standards in all of our products, and this drives stringent manufacturing testability requirements for all of our designs,'' said Philippe Magarshack, group vice president of STMicroelectronics' Central R&D for Design Automation. ``To meet these challenges, STMicroelectronics joined forces with Synopsys to combine our companies' complementary expertise in SoC design, tools and methodologies. This will enable us to effectively attack the challenges of ST's most complex system-on-chip DFT architectures, including on-chip BIST, scan, and interconnectivity testing.''

``It is extremely important for Synopsys, the leader in DFT automation, to work with the leading experts in system-on-chip design and production,'' said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test business unit. ``Partnering with STMicroelectronics gives us critical insight into next generation device challenges and the chance to respond quickly to the precise needs of a key driver in the system-on-chip arena. This relationship provides us the ability to further advance the robustness, productivity benefits and features set of our SoC DFT technology.''

DFT Closure -- The Next Step in IC Testability

DFT closure is the ability meet all mandated DFT requirements, rapidly and predictably, through every phase of a SoC design flow with no risk of iterations caused by unanticipated test impact. As ICs get more sophisticated, not embracing DFT closure methodologies will result in designs that may substantially miss market windows while still not meeting required functionality, performance and manufacturability goals.

DFT closure assumes a top-down hierarchical design approach that predictably proceeds from the RT-level, pre-synthesis planning, all the way to physical implementation. Traditional methodologies requiring design handoffs between discrete processes, such as between synthesis and scan insertion, are becoming intractable. In these traditional approaches, it is all too easy to lack knowledge and an understanding of integration issues between discrete design processes, which lead to schedule-killing iterations.

Synopsys' Versatile Test Solution

Synopsys, the leading supplier of IC test automation solutions, offers a complete line of integrated products and services that enable IC design teams to meet their most demanding manufacturing test requirements.

Synopsys' test offering includes DFT Compiler, incorporating the latest generation of Synopsys' patented 1-Pass test synthesis technology. DFT Compiler enables design teams to efficiently meet their DFT closure goals within Synopsys' industry-leading synthesis design flows. Additionally, to support increasingly complex board-level testing requirements, Synopsys offers BSD Compiler, an integrated boundary scan synthesis, IEEE 1149.1 compliance checking and boundary scan pattern generation solution. For advanced automatic test pattern generation requirements, Synopsys offers industry-leading TetraMAX(TM) ATPG family, a production-proven solution that simplifies test generation tasks by creating compact test patterns and providing advanced debug capabilities in an easy-to-use integrated graphical interface. Complementing these products, Synopsys offers comprehensive test services delivered by a world-class team of DFT experts.

About STMicroelectronics

STMicroelectronics (formerly SGS-THOMSON Microelectronics) is a global independent semiconductor company, whose shares are traded on the New York Stock Exchange, on the Bourse de Paris and on the Milan Stock Exchange. The Company designs, develops, manufactures and markets a broad range of semiconductor integrated circuits (ICs) and discrete devices used in a wide variety of microelectronics applications, including telecommunications systems, computer systems, consumer products, automotive products and industrial automation and control systems. Further information on ST can be found at http://www.st.com.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Synopsys is a registered trademark and Design Compiler and TetraMAX are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Synopsys
     Robert Smith, 650/584-1261
     rsmith@synopsys.com
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     Nancy Sheffield, 408/269-0849
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